1. Technical Field
The exemplary embodiment of the present invention relates to a write driver, a semiconductor memory apparatus using the same and a programming method.
2. Related Art
Phase-change random access memories (PCRAMs) which are a kind of non-volatile semiconductor memory devices, program data by applying a current to the memory devices. The PCRAMs have drawn attention by being able to provide performance better than DRAMs in terms of speed and a number of rewrites allowed.
FIG. 1 is a cross-sectional view of a conventional phase-change memory device.
Referring to FIG. 1, a phase-change memory device may include a semiconductor substrate 10 in which a bottom structure such as a switching device, or the like (not shown) is formed, a lower electrode 12 formed on the semiconductor substrate 10, a phase-change material layer 14 formed on the lower electrode 12, and an upper electrode 16 formed on the phase-change material layer 14.
The phase-change material layer is to be heated at a temperature above a melting point to place a phase-change memory cell in a reset state (e.g., an amorphous state). At this time, as illustrated in FIG. 2, a reset current of a simple square wave is applied for a time of about several hundred ns.
More specifically, a high current is applied continuously for a long time to reset a memory cell into the reset state. Here, heat generated at a cell to be programmed may transfer to an adjacent memory cell. At this time, the transferred heat may cause a disturbance in the adjacent cell to change its state
FIG. 3 is a diagram illustrating such a disturbance in resetting of a phase-change memory device.
A reset current having a profile shown in FIG. 2 is applied to the phase-change material layer 14 on a left-side lower electrode to make the phase-change material layer 14 to be in an amorphous state. The reference numeral 141 indicates an area having an amorphous state after applying the reset current.
However, when the reset current is applied to program the left-side cell, the accompanying heat may also be transferred to a phase-change material layer 14 on a right-side lower electrode. If the right-side cell is in the reset state, the transferred heat may cause an amorphous area 143 of the right-side cell to change into the crystalline state unintentionally.
Because of such features, a method which limits the reset current and shortens a reset current applying time have been considered.
FIG. 4 is a diagram illustrating an operation characteristic of the phase-change memory device where the reset pulse applying time has been reduced.
In the case where a reset pulse is applied for a short period time ranging from about 10 to 30 ns so as to prevent a disturbance causing unintended memory device state changes, any disturbance on adjacent cells can be reduced/minimized. However, the phase-change material layer may not be heated for a sufficient time and thus smaller amorphous areas 145 and 147 may result in a smaller reset resistance. Here, the reduction in the reset resistance causes a reset margin to be reduced for each cell where low heat generated at the cell may cause the stored data to be easily lost and thus degrade the operation reliability of a semiconductor memory device.
FIG. 5 is a graph illustrating a correlation between the reset pulse applying time and the reset resistance.
As illustrated in FIG. 5, the reset resistance becomes lowered as the reset pulse applying time becomes shorter. Here, the phase-change material layer is desired to be heated for a sufficient time enough for the subject phase-change memory cell to enter the reset state while not causing unintended degradation in states of the adjacent cells.